At present, various types of memories have been developed, e.g., a Random Access Memory (RAM), a Dynamic Random Access Memory (DRAM), a Read Only Memory (ROM), an Electrically Programmable Read Only Memory (EPROM), a FLASH memory, etc., as long with continued development of memory technologies.
The majority of semiconductor memories include various types of circuits, e.g., memory circuits and peripheral circuits. A typical flash memory includes arrays of memory cells, and these arrays of memory cells include a number of memory cells arranged in blocks. Each memory cell is fabricated as a field effect transistor including a control gate and a floating gate. The floating gate is used to store charges and separated from source and drain areas included in a substrate by a thin oxide layer. Such a memory cell can perform various operations including programming, reading, erasing, etc. For example, electrons may be injected on the floating gate from the drain area through the oxide layer to electrically charge the memory cell. During the erase operation, electrons are tunneled to the gate through the oxide layer in the prior art to thereby remove charges from the floating gate. Thus data in the memory cell is determined by presence or absence of charges on the floating gate.
FIG. 1 illustrates a schematic structural diagram of a conventional type of memory device. Referring to FIG. 1, the memory device includes two memory cells M1 and M2 formed on a P-type semiconductor substrate 100 in which there are formed a first diffusion area 120 and a second diffusion area 130, both of which are of N-type. The first diffusion area 120 is a common source area common to the two memory cells M1 and M2, and the second diffusion area 130 is a drain area. The memory cells M1 and M2 have a mirrored structure relative to the first diffusion area 120 (i.e. the common source area).
Specifically each of the memory cells M1 and M2 includes a channel area 140, a floating gate 150, a control gate 160, a gate insulating layer 170, and a poly-oxide layer 180 and an insulating oxide layer 190 formed on the floating gate 150, all of which are located between the first diffusion area 120 and the second diffusion area 130.
Particularly the floating gate 150 is an electrically isolated gate electrode and located on the semiconductor substrate 100 between the first diffusion area 120 and the second diffusion area 130, and has a first side partially overlapping with the first diffusion area 120. The control gate 160 is located on the semiconductor substrate 100 between a second side of the floating gate 150 and the second diffusion area 130. The insulating oxide layer 190 is located between the control gate 160 and the second side of the floating gate 150 and covers a sidewall of the floating gate 150 and a part of the channel area 140. The gate insulating layer 170 is located between the floating gate 150 and the semiconductor substrate 100 to insulate the floating gate 150 and the control gate 160 from the semiconductor substrate 100. And the poly-oxide layer 180 is formed on the floating gate 150 in a local oxidization of silicon (LOCOS) process.
In a conventional design, each control gate 160 is a Word Line (WL) (not illustrated in FIG. 1) extending in a row direction (the direction A-A′ as illustrated in FIG. 1) and is connected jointly in the row to the respective memory cell. An interlayer dielectric layer 110 is formed above the memory cells M1 and M2. A common source line 220 is connected to the first diffusion area 120 (the common source area) through a contact plug 210 and extends in the same direction as the control gate 160 (i.e., the word line). A connection node (not illustrated in FIG. 1) is formed on the second diffusion area 130 (the drain area) and connected through a Bit Line (BL) and extends in a column direction (the direction B-B′ as illustrated in FIG. 1).
In the memory device illustrated in FIG. 1, the two connection nodes in the memory cells M1 and M2 are connected jointly to the same bit line BL, so that the memory cells M1 and M2 share the same bit line. In this structure, the memory cells M1 and M2 are programmed respectively with the separate word lines, thus easily incurring crosstalk to another sub-memory cell located in the same column or row or diagonally with a programmed (selected) sub-memory cell.